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| M48T201Y M48T201V 3.3V-5V TIMEKEEPER(R) CONTROLLER s CONVERTS LOW POWER SRAMs into NVRAMs YEAR 2000 COMPLIANT BATTERY LOW FLAG INTEGRATED REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and CRYSTAL WATCHDOG TIMER WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T201Y: 4.1V VPFD 4.5V - M48T201V: 2.7V VPFD 3.0V 44 s s s SNAPHAT (SH) Battery/Crystal s s 1 SOH44 (MH) s PACKAGING INCLUDES a 44-LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE IN THE BATTERY BACKED-UP MODE s Figure 1. Logic Diagram s VCC s 19 A0-A18 WDI W E G RSTIN1 RSTIN2 M48T201Y M48T201V 8 DQ0-DQ7 IRQ/FT RST GCON ECON SQW VOUT DESCRIPTION The M48T201Y/201V are self-contained devices that include a real time clock (RTC), programmable alarms, a watchdog timer, and a square wave output which provides control of up to 512K x 8 of external low-power static RAM. Access to all RTC functions and the external RAM is the same as conventional bytewide SRAM. The 16 TIMEKEEPER (R) registers offer year, month, date, day, hour, minute, second, calibration, alarm, century, watchdog, and square wave output data. Externally attached static RAMs are controlled by the M48T201Y/201V via the GCON and ECON signals. The 44 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. November 1999 VSS AI02240 1/24 M48T201Y, M48T201V, Figure 2. SOIC Connections Table 1. Signal Names A0-A18 DQ0-DQ7 Address Inputs Data Inputs / Outputs Reset 1 Input Reset 2 Input Reset Output (Open Drain) Watchdog Input Chip Enable Input Output Enable Input Write Enable Input RAM Chip Enable Output RAM Enable Output Interrupt / Frequency Test Output (Open Drain) Square Wave Output Supply Voltage Output Supply Voltage Ground Not Connected Internally RSTIN1 RSTIN2 RST NC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 WDI GCON DQ0 DQ1 DQ2 VSS 1 44 43 2 3 42 4 41 40 5 6 39 7 38 8 37 9 36 10 35 11 34 M48T201Y 12 M48T201V 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 AI02241 VCC VOUT SQW IRQ/FT A17 A15 A13 A8 A9 A11 G W NC A10 E ECON DQ7 DQ6 DQ5 DQ4 DQ3 NC RSTIN1 RSTIN2 RST WDI E G W ECON GCON IRQ/FT SQW VOUT VCC VSS NC Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 44 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4Txx-BR12SH1" (See Table 14). Caution: Do not place the SANPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Automatic backup and write protection for an external SRAM is provided through VOUT, ECON, and GCON pins. (Users are urged to insure that voltage specifications, for both the controller chip and external SRAM chosen, are similar.) The SNAPHAT containing the lithium energy source used to permanently power the real time clock is also used to retain RAM data in the absence of VCC power through the VOUT pin. The chip enable output to RAM (ECON) and the output enable output to RAM (GCON) are controlled during power transients to prevent data corruption. The date is automatically adjusted for months with less than 31 days and corrects for leap years. The internal watchdog timer provides programmable alarm windows. The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORTTM read/write memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. 2/24 M48T201Y, M48T201V, Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG TSLD (2) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation M48T201Y M48T201V SNAPHAT SOIC Value 0 to 70 -40 to 85 -55 to 125 260 -0.3 to VCC+0.3 -0.3 to 7.0 -0.3 to 4.6 20 1 Unit C C C C V V V mA W Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPH AT sockets. Table 3. Operating Modes (1) Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO (2) (2) VCC 4.5V to 5.5V or 3.0V to 3.6V E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z D IN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode Note: 1. X = VIH or VIL. 2. VSO = Battery Back-up Swit chover Voltage. (See Tables 6A and 6B for details). Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the Watchdog Steering bit (WDS). Bytes 7FFF6h - 7FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition, the battery status and square wave output operation. 4-bits are included within this regis- ter (RS0-RS3) that are used to program the Square Wave Output Frequency (see Table 11). The M48T201Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. 3/24 M48T201Y, M48T201V, Figure 3. Block Diagram A0-A18 32,768 Hz CRYSTAL VOUT 0.1F 5V LITHIUM CELL M48T201Y/V VCC A0-Axx VCC 0.1F E W G WDI RSTIN1 RSTIN2 VSS GCON RST IRQ/FT SQW DQ0-DQ7 VSS DQ0-DQ7 ECON E W G CMOS SRAM AI00604 Figure 4. AC Testing Load Circuit Table 4. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V DEVICE UNDER TEST 645 Note that Output Hi-Z is defined as the point where data is no longer driven. CL = 100pF 1.75V CL includes JIG capacitance AI02330 Note: Excluding open-drain output pin. Address Decoding The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection of up to 512K bytes of static RAM. Regardless of SRAM density used, timekeeping, watchdog, alarm, century, flag, and control registers are located in the upper RAM locations. All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting the GCON (output enable RAM) signal during clock access. The RAM's physical locations are transparent to the user and the memory map looks continuous from the first clock address to the upper most attached RAM addresses. 4/24 M48T201Y, M48T201V, Table 5. Capacitance (1) (TA = 25 C, f = MHz) Symbol C IN CIO (2) Parameter Input Capacitance Input / Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. Outputs deselected. Table 6A. DC Characteristics (TA = 0 to 70 C; VCC = 3.0V to 3.6V) Symbol ILI (1, 2) ILO (1) ICC ICC1 ICC2 IBAT VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Battery Current OSC ON Battery Current OSC OFF Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (open drain) (3) Output High Voltage IOL = 2.1mA IOL = 10.0mA IOH = -1.0mA IOUT2 = -1.0A VOUT1 > VCC -0.3 VOUT2 > VBAT -0.3 2.9 VPFD- 100mV 3.0 2.7 2.4 2.0 3.6 70 100 3.0 -0.3 2.0 Test Condition 0V V IN VCC 0V VOUT VCC Outputs open E = VIH E = VCC -0.2V 575 4 Typ Min Max 1 1 10 3 2 800 100 0.8 VCC + 0.3 0.4 0.4 Unit A A mA mA mA nA nA V V V V V V mA A V V V VOHB (4) VOH (Battery Back-Up) IOUT1 (5) VOUT Current (Active) IOUT2 VPFD VSO VBAT Note: 1. 2. 3. 4. VOUT Current (Battery Back-Up) Power Fail Deselect Battery Back-Up Switchover Battery Voltage Outputs deselected. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. For IRQ/FT, RST pins (Open Drain). Conditioned outputs (ECON and GCON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will reduce battery lif e. 5. External SRAM must match TIMEKEE PER Controller chip VCC specification. 5/24 M48T201Y, M48T201V, Table 6B. DC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V) Symbol ILI (1, 2) ILO (1) ICC ICC1 ICC2 IBAT VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Battery Current OSC ON Battery Current OSC OFF Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (open drain) (3) Output High Voltage IOL = 2.1mA IOL = 10.0mA IOH = -1.0mA IOUT2 = -1.0A VOUT1 > VCC -0.3 VOUT2 > VBAT -0.3 4.35 3.0 3.0 4.1 2.4 2.0 3.6 100 100 4.5 -0.3 2.2 Test Condition 0V V IN VCC 0V VOUT VCC Outputs open E = VIH E = VCC -0.2V 575 8 Typ Min Max 1 1 15 5 3 800 100 0.8 VCC + 0.3 0.4 0.4 Unit A A mA mA mA nA nA V V V V V V mA A V V V VOHB (4) VOH (Battery Back-Up) IOUT1 (5) VOUT Current (Active) IOUT2 VPFD VSO VBAT Note: 1. 2. 3. 4. VOUT Current (Battery Back-Up) Power Fail Deselect Battery Back-Up Switchover Battery Voltage Outputs deselected. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100K resistor. For IRQ/FT, RST pins (Open Drain). Conditioned outputs (ECON and GCON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will reduce battery lif e. 5. External SRAM must match TIMEKEE PER Controller chip VCC specification. 6/24 M48T201Y, M48T201V, Figure 5. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tFB tRB tR tREC INPUTS VALID DON'T CARE VALID HIGH-Z OUTPUTS VALID VALID RST AI03519 Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C) Symbol tF tFB tR tRB tREC Parameter VPFD (max) to VPFD (min) VCC Fall Time M48T201Y VPFD (min) to VSS V CC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to RST High M48T201V Min 300 10 150 10 5 40 200 Max Unit s s s s s ms 7/24 M48T201Y, M48T201V, Figure 6. GCON Timing When Switching Between RTC and External SRAM ADDRESS 7FFF0h - 7FFFFh 00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh G GCON tAOEL E tAOEH tOERL tRO AI02333 Table 8. Read Mode AC Characteristics (TA = 0 to 70 C) M48T201Y Symbol Parameter Min tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX tAOEL tAOEH tEPD t OERL t RO Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition External SRAM Address to GCON Low Controller SRAM Address to GCON High E to ECON Low or High G Low to GCON Low G High to GCON High 5 20 20 10 15 10 5 0 20 20 5 30 30 15 20 15 70 70 70 25 5 0 25 25 -70 Max Min 85 85 85 35 M48T201V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 8/24 M48T201Y, M48T201V, Figure 7. Read Cycle Timing: RTC & External RAM Control Signals READ tAVAV ADDRESS tELQV E tELQX G tGLQV READ tAVAV WRITE tAVAV tAVQV tAVWL tWHAX tRO GCON ECON tEPD W tWLWH tGLQX tAXQX tGHQZ DQ0-DQ7 DATA OUT VALID DATA OUT VALID DATA IN VALID AI02334 READ MODE The M48T201Y/V executes a read cycle whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the address inputs (A0-A18) defines which one of the on-chip TIMEKEEPER registers or external SRAM locations is to be accessed. When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of the on-board TIMEKEEPER registers is accessed and valid data will be available to the eight data output drivers within tAVQV after the address input signal is stable, providing that the E and G access times are also sat- isfied. If they are not, then data access must be measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the address access time. When one of the on-chip TIMEKEEPER registers is selected for read, the GCON signal will remain inactive throughout the read cycle. When the address value presented to the M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location will be selected. In this case the G signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL. 9/24 M48T201Y, M48T201V, Figure 8. Write Cycle Timing: RTC & External RAM Control Signals WRITE tAVAV ADDRESS tAVEH tAVEL E tEPD ECON tEPD G tRO GCON tAVWL W tEHQZ DQ0-DQ7 DATA OUT VALID WRITE tAVAV READ tAVAV tAVWH tEHAX tWHAX tAVQV tELEH tGLQV tEHDX tWLWH tWHQX tWLQZ tDVEH DATA IN VALID tDVWH DATA IN VALID tWHDX DATA OUT VALID AI02336 WRITE MODE The M48T201Y/V is in the Write Mode whenever W (Write Enable) and E (Chip Enable) are low state after the address inputs are stable. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. When the address value presented to the M48T201Y/V during the write is in the range of 7FFFFh-7FFF0h, one of the on-board TIMEKEEPER registers will be selected and data will be written into the device. When the address value presented to M48T201Y/V is outside the range of TIMEKEEPER registers, an external SRAM location is selected. 10/24 M48T201Y, M48T201V, Table 9. Write Mode AC Characteristics (TA = 0 to 70 C) M48T201Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX t EHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High 55 55 5 70 0 0 45 50 0 0 25 25 0 0 20 65 65 5 -70 Max Min 85 0 0 55 60 0 0 30 30 0 0 25 M48T201V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tWHQX (1, 2) Write Enable High to Output Transition Note: 1. CL = 5pF. 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. DATA RETENTION MODE With valid VCC applied, the M48T201Y/V can be accessed as described above with read or write cycles. Should the supply voltage decay, the M48T201Y/V will automatically deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD (max) and VPFD (min). This is accomplished by internally inhibiting access to the clock registers via the E signal. At this time, the Reset pin (RST) is driven active and will remain active until V CC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is within 0.2V of the VBAT. ECON will remain at this level as long as VCC remains at an out-of tolerance condition. When VCC falls below the level of the battery (VBAT), power input is switched from the VCC pin to the SNAPHAT battery and the clock registers are maintained from the attached battery supply. External RAM is also powered by the SNAPHAT battery. All outputs except GCON, ECON, RST, IRQ/FT and VOUT, become high im- pedance. The VOUT pin is capable of supplying 100A of current to the attached memory with less than 0.3V drop under this condition. On power up, when VCC returns to a nominal value, write protection continues for 200ms (max) by inhibiting ECON. The RST signal also remains active during this time (see Figure 5). Note: Most low power SRAMs on the market today can be used with the M48T201Y/V TIMEKEEPER Controller. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be Don't Care once VCC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0V. The chip enable access time must be sufficient to meet the system needs with the chip enable (and output enable) output propagation delays included. 11/24 M48T201Y, M48T201V, Figure 9. Alarm Interrupt Reset Waveforms A0-A18 ADDRESS 7FFF0h 15ns Min ACTIVE FLAG BIT IRQ/FT HIGH-Z AI02331 Table 10. Alarm Repeat Modes RPT5 1 1 1 1 1 RPT4 1 1 1 1 0 RPT3 1 1 1 0 0 RPT2 1 1 0 0 0 RPT1 1 0 0 0 0 Alarm Activated Once per Second Once per Minute Once per Hour Once per Day of Month Once per Month If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which val- ue to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M48T201Y/V to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT of your choice can then be divided by this current to determine the amount of data retention available (see Table 14). For a further more detailed review of lifetime calculations, please see Application Note AN1012. 12/24 M48T201Y, M48T201V, Figure 10. Back-Up Mode Alarm Waveform tREC VCC VPFD (max) VPFD (min) VSO AFE bit/ABE bit AF bit in Flags Register IRQ/FT HIGH-Z AI03520 HIGH-Z TIMEKEEPER REGISTERS The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER, Alarm, Watchdog, Interrupt, Flag, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers store data in BCD. Control, Watchdog and Flags (bits D0 to D3) Registers store data in Binary Format. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the Control Register (7FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs approximately 1 second after the READ bit is reset to a ` 0'. Setting the Clock Bit D7 of the Control Register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 12). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh-7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur approximately one second later. Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to '0'. 13/24 M48T201Y, M48T201V, Table 11. Square Wave Output Frequency (TA = 0 to 70C) Square Wave Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency Hi-Z 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at Bit D7 within the Seconds Register (7FFF9h). Setting it to a '1' stops the oscillator. When reset to a '0', the M48T201Y/V oscillator starts within one second. Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). SETTING ALARM CLOCK Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, day of month, hour, minute, or second or repeat every month, day of month, hour, minute, or second. It can also be programmed to go off while the M48T201Y/V is in the battery back-up to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 10 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see Flag bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm, write '0' to the Alarm-Date register and RPT1-4. The IRQ/FT output is cleared by a read to the Flags register as shown in Figure 9. A subsequent read of the Flags register will reset the Alarm Flag (D6; Register 7FFF0h). The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T201Y/V was in the deselect mode during power-up. Figure 10 illustrates the back-up mode alarm timing. 14/24 M48T201Y, M48T201V, Table 12. Register Map Data Address D7 7FFFFh 7FFFEh 7FFFDh 7FFFCh 7FFFBh 7FFFAh 7FFF9h 7FFF8h 7FFF7h 7FFF6h 7FFF5h 7FFF4h 7FFF3h 7FFF2h 7FFF1h 7FFF0h Keys: D6 D5 D4 D3 D2 Year D1 D0 Function/Rang e BCD Format Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59 10 Years 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 R BMB4 SQWE RPT5 0 0 0 FT 0 0 10 M Month Date: Day of Month 0 Day Hours (24 Hour Format) Minutes Seconds Calibration 10 Date 0 0 10 Hours 10 Minutes 10 Seconds S BMB3 ABE BMB2 Al.10M BMB1 BMB0 RB1 RB0 Watchdog Al. Month Al. Date Al. Hours Al. Minutes Al. Seconds Century 01-12 01-31 00-23 00-59 00-59 00-99 Alarm Month Alarm Date Alarm Hours Alarm Minutes Alarm Seconds 100 Years Al. 10 Date Al. 10 Hours Alarm 10 Minutes Alarm 10 Seconds 1000 Years WDF AF 0 BL RS3 RS2 RS1 RS0 Flags S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to zero Z = '0' and are Read only WDS = Watchdog Steering Bit AF = Alarm Flag BL = Battery Low SQWE = Battery Low Flag BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog Flag RS0-RS3 = SQW Frequency WATCHDOG TIMER The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 7FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds). Note: Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T201Y/V sets the WDF (Watchdog Flag) and generates a watchdog inter- rupt or a microprocessor reset. WDF is reset by reading the Flag Register (Address 7FFF0h). The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a '0', the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1', the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The Watchdog register and the FT bit will reset to a '0' at the end of a Watchdog time-out when the WDS bit is set to a '1'. The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI) or 2) the microprocessor can perform a write of the Watchdog Register. The time-out period then starts over. The WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) seen by the WDI pin. 15/24 M48T201Y, M48T201V, Figure 11. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register will reset the Watchdog Flag (Bit D7; Register 7FFF0h). The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. Square Wave Output The M48T201Y/V offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency. These frequencies are listed in Table 11. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in Register 7FFF6h. POWER-ON RESET The M48T201Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40 to 200ms after VCC passes VPFD. The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control rise time. Reset Inputs (RSTIN1 & RSTIN2) The M48T201Y/V provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle. Table 13 and Figure 12 illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100K resistor. Calibrating the Clock The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M48T201Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11. 16/24 M48T201Y, M48T201V, Table 13. Reset AC Characteristics (TA = 0 to 70C, VCC = 3.0V to 3.6V or VCC = 4.5V to 5.5V) Symbol tR1 tR2 tR1HRZ (1) tR2HRZ (1) Parameter RSTIN1 Low to RST Low RSTIN2 Low to RST Low RSTIN1 High to RST Hi-Z RSTIN2 High to RST Hi-Z Min 50 20 40 40 Max 200 100 200 200 Unit ns ms ms ms Note: 1. 1.CL = 5pF. Table 14. SNAPHAT Battery Table Part Number M4T28-BR12SH M4T32-BR12SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T201Y/V may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in STMicroelectronics Application Note: TIMEKEEPER CALIBRATION. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 7FFF9h) is '0',the Frequency Test bit (FT, D6 of 7FFFCh) is '1', the Alarm Flag Enable bit (AFE, D7 of 7FFF6h) is '0', and the Watchdog Steering bit (WDS, D7 of 7FFF7h) is '1' or the Watchdog Register (7FFF7h=0) is reset. Note: A 4 second settling time must be allowed before reading the 512Hz output. Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a -12 (001100) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-up. 17/24 M48T201Y, M48T201V, Figure 12. RSTIN1 and RSTIN2 Timing Waveforms RSTIN1 RSTIN2 tR2 Hi-Z RST tR1 tR1HRZ tR2HRZ AI01679 Hi-Z BATTERY LOW WARNING The M48T201Y/V automatically performs battery voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24 hours. The Battery Low (BL) bit, Bit D4 of Flags Register 7FFF0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while VCC is applied to the device (Note, this will cause the clock to lose time during the time interval the battery/crystal is removed). The M48T201Y/201V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 18/24 M48T201Y, M48T201V, POWER-ON DEFAULTS Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R; FT. (See Table 15) POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Table 15. Default Values Conditi on Initial Power-up (Battery Attach for SANPHAT) (2) Subsequent Power-up / RESET (3) Power-down (4) Note: 1. 2. 3. 4. Figure 13. Supply Voltage Protection VCC VCC 0.1F DEVICE VSS AI00605 W 0 0 0 R 0 0 0 FT 0 0 0 AFE 0 0 1 AFE 0 0 1 WATCHDOG Register (1) 0 0 0 WDS, BMB0-BMB4, RB0, RB1. State of other control bits undefined. State of other control bits remains unchanged. Assuming these bits set to `1' prior to power-down. 19/24 M48T201Y, M48T201V, Table 16. Ordering Information Scheme Example: Device Type M48T Supply Voltage and Write Protect Voltage Y = VCC = 4.5V to 5.5V; V PFD = 4.1V to 4.5V V = VCC = 3.0V to 3.6V; V PFD = 2.7V to 3.0V Speed -70 = 70ns (M48T201Y) -85 = 85ns (M48T201V) Package MH (1) = SOH44 Temperature Range 1 = 0 to 70 C Shipping Method for SOIC blank tubes TR Tape & Reel M48T201Y -70 MH 1 TR Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4TxxBR12SH1" in plastic tube or "M4Txx-BR12SH1TR" in Tape & Reel form. Caution:Do not place the SNAPHAT battery package "M4Txx-BR12SH1" in conductive foam since will drain the lithium button-cell battery. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 20/24 M48T201Y, M48T201V, Table 17. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Mechanical Data mm Symb Typ A A1 A2 B C D E e eB H L N CP 0.81 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 44 0.10 Min Max 3.05 0.36 2.69 0.46 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.032 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 44 0.004 Typ Min Max 0.120 0.014 0.106 0.018 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches Figure 14. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline A2 B e A C eB CP D N E H A1 L 1 SOH-A Drawing is not to scale. 21/24 M48T201Y, M48T201V, Table 18. SH - 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches Figure 15. SH - 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline A1 A2 A A3 eA D B eB L E SHTK-A Drawing is not to scale. 22/24 M48T201Y, M48T201V, Table 19. SH - 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches Figure 16. SH - 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline A1 A2 A A3 eA D B eB L E SHTK-A Drawing is not to scale. 23/24 M48T201Y, M48T201V, Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com 24/24 |
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